1. Field
Exemplary embodiments of the present invention relate to an address comparator circuit, a memory device including the same, and a memory system including the memory device.
2. Description of the Related Art
A memory device stores external data and outputs the stored data. The memory device includes data input/output (I/O) lines along which data is transmitted. The data I/O lines include a global I/O line that transfers data between a data I/O pad and memory banks and that is shared by the memory banks and local I/O lines included in the respective memory banks. The transfer of data in a memory device is described below.
FIG. 1 is a diagram schematically illustrating the data I/O path of a memory device.
A write operation in which external data is received is described. Data inputted through a data pad DQ is loaded onto a global I/O line GIO via a reception circuit 102. When a first bank 110 is selected, the data on the global I/O line GIO is loaded onto the local I/O line pair LIO_B0 and LIOb_B0 coupled to the first bank 110 by a write driver 112. The data loaded onto the local I/O line pair LIO_B0 and LIOb_B0 is written in a selected memory cell within the first bank 110. When the second bank 120 is selected, the data of the global I/O line GIO is loaded onto the local I/O line pair LIO_B1 and LIOb_B1 of the second bank 120 by the write driver 122 and then written in a selected memory cell within the second bank 120.
A read operation in which data is output by a memory device is described below. When the first bank 110 is selected, data stored in a selected memory cell within the first bank 110 is loaded onto the local I/O line pair LIO_B0 and LIOb_B0, and then loaded onto the global I/O line GIO amplified by an I/O sense amp 111. The data on the global I/O line GIO is output to the outside of the memory device by a transmission circuit 101. When the second bank 120 is selected, data stored in a selected memory cell within the second bank 120 is output to the outside of the memory device through the local I/O line pair LIO_B1 and LIOb_B1, an I/O sense amp 121, the global I/O line GIO, and the transmission circuit 101.
FIG. 2 is a diagram illustrating an active operation and a read operation of a word line and a bit line. FIG. 2 shows a problem occurring when the read operation is repeatedly performed on a single memory cell.
Referring to FIG. 2, at a first point of time 201, the word line WL is activated in response to an active command. When the word line WL is activated, the data of a memory cell corresponding to the word line WL is loaded onto a bit line pair BL and BLb. As shown in FIG. 2, a voltage level of the primary bit line BL is higher than that of the secondary bit line BLb due to charge sharing between the memory cell and the bit line pair BL and BLb. At a second point of time 202, a bit line sense amp is activated, and a small potential difference between the bit line pair BL and BLb is amplified by the bit line sense amp. As a result, the primary bit line BL has the same level as a core voltage VCORE, i.e., a voltage of a high level used in a cell region, and the secondary bit line BLb has the same level as a ground voltage VSS.
Third to fifth points of time 203 to 205 denote sections in each of which a read operation is performed in response to a read command. In the section in which the read operation is performed, the voltage level of the bit line pair BL and BLb is transferred to the local I/O line pair LIO and LIOb. That is, the local I/O line pair LIO and LIOb may be driven by the bit line pair BL and BLb. Accordingly, the voltage level of the primary bit line BL drops, and the voltage level of the secondary bit line BLb rises. The changed voltage level of the bit line pair BL and BLb recovers to the original level by a sense amp. When the above-described read operations are consecutively repeated during the sections denoted by the third to fifth points of time 203, 204, and 205 as shown in FIG. 2, the voltage level of the bit line pair BL and BLb does not recover to the original level and the voltage difference between the bit line pair BL and BLb is gradually reduced. As a result, the voltage levels of the bit line pair BL and BLb are reversed as shown in the last section denoted by the fifth point of time 205, which cause a read fail.
The consecutive repetition of read operations is frequently performed on the same memory cell while a memory device operates. Accordingly, there is a need to prevent fails that are attributable to the consecutive repetition of read operations on the same memory cell.